基于1/4速率架构的60Gb/s PAM4信号SerDes接收端设计

Design on the 60Gb/s PAM4 Signal SerDes Receiver Based on 1/4 Rate Architecture

摘要:

随着信息技术的不断发展，通信系统对数据传输速率提出了更高的要求。为了扩展高频带宽同时降低电路功耗，设计一种用于接收1/4速率架构的60Gb/s PAM4信号SerDes接收端。提出跨导跨阻抗（Gm-TIA）结构的连续时间线性均衡器（CTLE）和并行四抽头前馈均衡器（4-tap FFE）的均衡策略扩展高频带宽，采用四分之一速率结构进一步降低电路功耗。电路基于28nm CMOS工艺实现，在1.05/1.2V电源电压下，后仿真结果表明：在奈奎斯特15GHz频率处，CTLE可补偿18.5dB的信道衰减；经过4-tap FFE眼宽为0.6UI，眼高为120mV；整体接收端功耗为83.71mW，能效为1.40 pJ/bit，版图核心面积为394.55um*343.53um，所提电路适用于高速串行接口和通信应用中。

Abstract:

With the continuous development of information technology, communication systems require higher data transmission rates. In order to extend the high-frequency bandwidth and reduce the circuit power consumption at the same time, a 60Gb/s PAM4 signal SerDes receiver for receiving 1/4 rate architecture is designed. A continuous time linear equalizer (CTLE) with transconductance trans-impedance amplifier (Gm-TIA) structure and a parallel four-tap feed forward equalizer (4-tap FFE) equalisation strategy are proposed to extend the high-frequency bandwidth, and a quarter-rate structure is used to further reduce the circuit power consumption. The circuit is implemented based on a 28nm CMOS process at 1.05/1.2V supply voltage, and post-simulation results show that: the CTLE compensates for 18.5dB of channel fading at Nyquist's 15GHz frequency; after a 4-tap FFE eye width of 0.6UI and an eye height of 120mV; the overall receiver-side power consumption is 83.71 mW, with an energy efficiency of 1.40 pJ/bit The proposed circuit has a core area of 394.55um*343.53um and is suitable for high-speed serial interface and communication applications.