基于ADC结构的56Gb/s PAM4信号SerDes接收端的设计

Design of a 56 Gb/s PAM4 Signal SerDes Receiver Based on ADC Structure

摘要:

基于28nm CMOS工艺，1.05/1.2V电源电压，采用32路时间交织ADC（TI-ADC）结构，设计了一种56 Gb/s 四电平脉冲（PAM4）信号的SerDes接收端。为了满足TI-ADC对输入信号的要求，提出了一种基于前馈结构的连续时间线性均衡器（CTLE）结合可变增益放大器（VGA）的模拟前端（AFE），在不影响低频增益的前提下提高高频增益。TI-ADC中的子ADC（sub ADC）采用一种一步两位逐次逼近模数转换器（2b/cycle SAR ADC），采样率为875MS/s分辨率为8bit。为保证共模输出电压以及减小建立时间，电容阵列DAC采用上级板采样的分裂电容结构；采用锁存式SAR 逻辑单元代替传统的静态触发器式移位寄存器，提高转换速度。仿真结果表明：在奈奎斯特14GHz频率下，CTLE补偿10.2dB信道衰减；VGA提升3dB低频增益，眼宽为0.37UI，眼高为150mV；TI-ADC采样速度28GS/s，SFDR为52.2dB，SNDR为45.8dB，ENOB为7.32bit；整体接收端功耗为344 mW，能效为6.14pJ/bit。

Abstract:

Based on a 28nm CMOS process with a 1.05/1.2V power supply, a 56 Gb/s four-level pulse amplitude modulation (PAM4) SerDes receiver has been designed using a 32-channel time-interleaved ADC (TI-ADC) structure. To meet the input signal requirements of the TI-ADC, an analog front-end (AFE) combining a feedforward continuous-time linear equalizer (CTLE) with a variable gain amplifier (VGA) is proposed. This approach enhances high-frequency gain without affecting low-frequency gain. The sub-ADC in the TI-ADC employs a one-step, two-bit successive approximation register (2b/cycle SAR ADC) with a sampling rate of 875 MS/s and a resolution of 8 bits. To ensure common-mode output voltage and reduce setup time, a split-capacitor structure is used for the capacitor array DAC sampled on the upper board. A latch-based SAR logic unit is employed instead of traditional static flip-flop shift registers to improve conversion speed. Simulation results indicate that at a Nyquist frequency of 14 GHz, the CTLE compensates for 10.2 dB of channel attenuation; the VGA increases low-frequency gain by 3 dB, with an eye width of 0.37 UI and an eye height of 150 mV. The TI-ADC achieves a sampling speed of 28 GS/s, with an SFDR of 52.2 dB, an SNDR of 45.8 dB, and an ENOB of 7.32 bits. The overall receiver power consumption is 344 mW, with an energy efficiency of 6.14 pJ/bit.