具有P-top层与缓冲层结构LDMOS击穿特性研究

LDMOS Breakdown with P-top Layer and Buffer Layer Structure

摘要:

在传统平面栅LDMOS结构(CON-LDMOS)基础上,设计了一种具有P-top层与N型缓冲层结构的LDMOS(BP-LDMOS)。P-top层辅助耗尽漂移区,拓宽了耗尽层宽度,并缓解了栅极右侧拐角处的电场集中效应,使横向电场分布更加均匀,器件耐压特性变好；N型缓冲层的设计,增大了漂移区内载流子密度,使器件导通特性得到了改善。本文主要探究了P-top层掺杂浓度、长度、厚度以及漂移区掺杂浓度对BP-LDMOS击穿特性的影响。仿真结果表明,相较于CON-LDMOS,BP-LDMOS击穿电压为329.4 V,提升了3 %；比导通电阻为23.1 mΩ·cm2,降低了40.1 %；品质因数为4.70 MW/cm2,提升了77.4 %。

Abstract:

Based on the traditional planar gate LDMOS structure (CON-LDMOS), an LDMOS (BP-LDMOS) structure with P-top layer and N-type buffer layer is designed. The P-top layer assists the depletion drift zone, broadening the depletion layer width, alleviating the electric field concentration effect at the right corner of the grid, and making the transverse electric field distribution more uniform. Better voltage resistance of the device; The design of N-type buffer layer increases the carrier density in the drift zone and improves the conduction characteristics of the device. In this paper, the influence of P-top layer doping concentration, length, thickness and drift zone doping concentration on the breakdown characteristics of BP-LDMOS is studied. The simulation results show that compared with CON-LDMOS, the breakdown voltage of BP-LDMOS is 329.4 V, which is 3 % higher, the specific on-resistance is 23.1 mΩ·cm2, which is 40.1 % lower, and the quality factor FOM is 4.70 MW/cm2, which is 77.4 % higher.