In the face of long transmission distance and high bit error rate caused by serious channel attenuation, the non-return-to-zero (NRZ) code signal is usually processed by forward feedback equalization (FFE) at the high-speed SerDes transmitter. Based on the UMC 28 nm CMOS process, a parallel configurable FFE high-speed serial interface (SerDes) transmitter is designed using an 8-bit digital-to-analog converter (DAC) architecture. The parallel input signal and the stored 8 10 bit tap coefficients are logically operated by the multiplier module and the parallel carry adder module in the configurable FFE to realize the signal pre-equalization processing. A high-speed 4 : 1 multiplexer (MUX) composed of AND-NOT gate, cascode device and reset path is adopted. The terminal output network adopts source series termination (SST) structure to achieve lower power loss. The simulation results show that when the transmitter is powered by 1.05 V voltage and the channel attenuation is 18.59 dB @ 20 GHz, the eye height of the output 40 Gb / s NRZ signal is 378.4 mV, the eye width is 18.53 ps (0.74 UI), the overall layout area is 0.055 mm2, and the overall circuit power consumption is 0.055 mm2, the power consumption of the whole circuit is 41.8 mW.
