一种4H-SiC超结UMOSFET的UIS特性分析

UIS Characteristics Analysis of a 4H-SiC Superjunction UMOSFET

摘要:

设计并优化了一种具有两段不同P柱浓度的4H-SiC超结沟槽型场效应晶体管结构(DP-SJ-UMOS)，分析了器件UIS测试电路与基本原理，利用Sentaurus TCAD仿真软件对该器件结构的UIS特性进行了详细研究，提出了三种提升雪崩耐量的方法。在漂移区采用多次外延生长与高能离子注入的方法形成上下两段不同浓度的超结结构，改善了器件雪崩击穿时的雪崩电流路径，使得击穿时流径器件寄生三极管的电流减小，有效抑制了寄生三极管的开启，提高了雪崩耐量。实验仿真表明，本文结构相较于传统超结器件(Con-SJ-UMOS)雪崩击穿电压提升了24.5%，峰值电流提升了4.8%，雪崩耐量提升了6.9%。

Abstract:

This study focuses on designing and optimizing a 4H-SiC superjunction trench field-effect transistor structure (DP-SJ-UMOS) with two segments of different P-pillar concentrations. Analyzed the device's UIS testing circuit and fundamental principles. Conducted a detailed study of the UIS characteristics of this device structure using Sentaurus TCAD simulation software, proposing three methods to improve avalanche tolerance. Employed multiple epitaxial growth and high-energy ion implantation techniques in the drift region to form the upper and lower segments of the superjunction structure with different concentrations, enhancing the avalanche current path during avalanche breakdown. This modification reduced the current of the parasitic transistor during breakdown, effectively suppressing the activation of the parasitic transistor and improving avalanche tolerance. Experimental simulations indicate that the proposed structure, compared to conventional superjunction devices(Con-SJ-UMOS), achieves a 4.8% increase in peak current while breakdown voltage increased by 24.5%, and a 6.9% enhancement in avalanche tolerance.