可配置分段式FFE高速SerDes发送端设计

Design of A Configurable Segmented FFE High-Speed SerDes Transmitter

摘要:

基于28nm CMOS工艺实现56Gb/s NRZ和112Gb/s PAM-4双模发送端设计,均衡采用一个数据多路复用架构,支持完全可配置的分段式前向反馈均衡(FFE),终端输出网络采用带有上拉电流源的电流模式逻辑(CML)驱动拓扑结构。关键的电路结构和技术包括:依靠段落分配模块对FFE的段落进行分配,实现抽头权重的粗调；采用预充型1-UI脉冲发生器+4∶1 MUX架构改善带宽；驱动器采用负载端并接电流源提升共模电压和插入T形线圈的方法来扩展输出带宽和提高输出摆幅。仿真结果表明在输出112Gb/sPAM4情况下眼高为40mV,56Gb/s NRZ情况下为130mV。

Abstract:

In this study, we implemented a 56Gb/s NRZ and 112Gb/s PAM-4 dual-mode transmitter design on a 28nm CMOS process. For the equalization, we used a data multiplexing architecture to support a fully configurable segmented feed-forward equalizer (FFE). Next, we adopted a current-mode logic (CML) driver topology, with a pull-up current source, as the terminal output network. The key circuit structures and techniques included relying on a paragraph allocation module to allocate paragraphs for the FFE and achieving coarse adjustments of the tap weights. We utilized a pre-charged 1-UI pulse generator and 4∶1 MUX to enhance the bandwidth. The driver incorporated a load-side parallel current source to boost the common-mode voltage and a T-coil to extend the output bandwidth and swing. Our simulation results demonstrated that the eye heights for the 112Gb/s PAM4 and 56Gb/s NRZ output were 40 and 130mV, respectively.