一种用于CIS列级ADC的片上抗PVT变化高精度自适应斜坡发生器

An On-Chip High Precision Adaptive Ramp Generator with Anti-PVT-Variation for CIS Column-Level ADC

摘要:

传统的片上全局斜坡发生器电路容易受工艺、电压和温度(PVT)的影响,导致斜坡信号易失真、线性度差；由于寄生电容的影响,片外校准的难度较大。提出了一种可以抗PVT变化,实现自适应校准斜率的斜坡发生器,采用逐次逼近算法细调和定步长搜索法微调相结合的方式,实现对斜坡的两点校正。斜坡校准电路包括电阻型DAC、电流型DAC、逻辑控制、动态比较器等模块。仿真结果表明,自适应斜坡发生器的平均校准周期约为1.143ms,校准后斜坡微分非线性为+0.00207/-0.00115LSB,积分非线性为+0.6755/-0.3887LSB,在不同PVT条件下校准电压误差小于1.5LSB,平均功耗仅为1.155mW,与传统斜坡发生器相比具有精度高、功耗低的优点。

Abstract:

The traditional on-chip global ramp generator circuit is significantly affected by process, voltage, and temperature (PVT), resulting in ramp signal distortion and poor linearity. Moreover, calibration becomes difficult owing to parasitic effects. Therefore, in this study, we introduced an adaptive ramp generator that resists PVT variations. We fine-tuned the ramp using a successive approximation algorithm and a fixed-step search method and achieved a two-point slope correction. The ramp calibration circuit included a resistive DAC (RDAC), current-mode DAC (IDAC), logic control, dynamic comparator, and other modules. The average calibration period for the adaptive ramp generator was found to be approximately 1.143ms. Post calibration, DNL of the adaptive ramp generator was +0.00207/-0.00115LSB and INL was +0.6755/-0.3887LSB. Under various PVT conditions, the calibration voltage error was less than 1.5LSB and power consumption was as low as 1.155mW. Compared with traditional ramp generators, the proposed adaptive generator is advantageous in terms of higher precision and lower power consumption.