Abstract:This article introduces a timing method for solving the accumulation of signals within CCD, which allows charges to accumulate in the vertical CCD summing gate and Floating Diff usion Amplifier. Thus, without increasing the vertical well depth and minimizing the horizontal well depth,The goal is to achieve greater charge transfer and readout. This timing method combines vertical and horizontal driving timing to achieve multi-level vertical timing.The superposition of straight signals and multi-level horizontal signals, especially the optimization and verification of the timing in the horizontal CCD direction, has achieved convenience.Improvement of CDS sampling in AD. This sequence has been successfully applied to aerospace in orbit models, achieving a large dynamic range of CCD devices.The output of analog image signals breaks through the limitation of process on pixel charge capacity.
