基于SAR ADC的短波红外焦平面数字化读出电路研究

Research on Short-Wave IRFPA digital readout circuit based on SAR ADC

摘要:

片上集成数字化是红外焦平面的主要发展方向之一，其关键技术是在读出电路内部集成模数转换ADC模块。针对线列InGaAs焦平面的数字化需求，采用了一种基于非二进制的冗余位 SAR ADC设计方案。整个读出电路包括读出电路单元和模数转换单元。读出电路单元采用的是CTIA的结构，其结构线性度好，注入效率高。模数转换单元采用的是SAR ADC，其结构简单，功耗低。本文采用非二进制校准的方法对CDAC模块进行设计，通过在电容阵列中插入冗余位来提高ADC的转换速度和精度，并使用下极板采样技术来提高采样精度。在0.18μm CMOS工艺模型下，完成了14bit的SAR ADC的设计。仿真结果表明：在采样率为1MSPS条件下，SAR ADC的信噪比SNR为74dB，有效位数为13.4bits。

Abstract:

On-chip integrated digitization is one of the main development directions of the infrared focal plane array, and its key technology is the integration of analog-to-digital conversion ADC blocks in the readout circuit. In response to the digitization requirements of the line linear InGaAs focal plane, a non-binary redundant bit SAR ADC design is adopted in this paper. The entire readout circuit includes a readout circuit unit and an analog-to-digital conversion unit. The readout circuit unit adopts the structure of CTIA, which has good structural linearity and high injection efficiency. The analog-to-digital conversion unit uses a SAR ADC, which has a simple structure and low power consumption. In this paper, the CDAC module is designed using a non-binary calibration method. In this paper, the CDAC module is designed using a non-binary calibration method. Which inserting redundant bits in the capacitor array to increase the conversion speed and accuracy of the ADC, and the sampling accuracy is improved using the bottom plate sampling technique. A 14-bit SAR ADC was designed and simulated with 0.18μm CMOS process model. At a sampling rate of 1MSPS, the SNR is 74dB and the ENOB is 13.4bits