基于测试结构的FinFET-MOS寄生电阻抽取

Extraction parasitic resistance of FinFET-MOS based on Test structure

摘要:

由于3D FinFET器件复杂的寄生效应所带来的影响逐渐接近甚至超过本征特性，精确快速的提取寄生电阻对于工艺优化、电路设计具有重要意义。本文基于14nm FinFET工艺合理设计了用于抽取源漏寄生电阻的测试结构，考虑到实际工艺限制，因此采用校准后的TCAD仿真分析结果作为理论支撑，通过98组不同尺寸的MOS器件测试数据实现了对14nm FinFET器件源漏寄生电阻的分解和抽取，抽取结果将分为三个部分:由源漏端的接触金属（M0层）、接触孔（VIA0）及引出金属（M1层）所引入的寄生成分; 栅侧墙和隔离层介质下的源漏扩展寄生成分; 重掺杂凸起源漏区域（EPI）寄生成分。最后，将TCAD仿真分析结果作为支撑与实测数据抽取结果比对，验证了测试结构方案的合理性和准确性。此方案将显著提高业界基于BSIM-CMG的模型提取工作的准确度。

Abstract:

Since the influence of the complex parasitic effects of 3D FinFET devices gradually approaches or even exceeds the intrinsic characteristics, accurate and rapid extraction of parasitic resistance is of great significance for process optimization and circuit design. In this paper, based on the 14nm FinFET process, the test structure for extracting the source-drain parasitic resistance is reasonably designed. Considering the actual process constraints, the calibrated TCAD simulation analysis results are used as theoretical support. For the decomposition and extraction of the source-drain parasitic resistance of 14nm FinFET devices, the extraction results will be divided into three parts: the parasitic components introduced by the contact metal (M0 layer), the contact hole (VIA0) and the extraction metal (M1 layer) of the source and drain terminals Rcon; source-drain extension parasitic component Rext which under gate spacer and isolation layer dielectric; parasitic component Repi of heavily doped raised source-drain region (EPI). Finally, the TCAD simulation analysis results are used as the support to compare with the measured data extraction results, which verifies the rationality and accuracy of the test structure scheme. This solution will significantly improve the accuracy of BSIM-CMG-based model extraction in the industry.