基于SAR-SS架构的图像传感器专用高速列级ADC设计

Design of high-speed column-level ADC for image sensor based on SAR-SS architecture

摘要:

针对图像传感器中传统列级模数转换器(ADC)难以实现高帧频的问题,提出了一种由逐次逼近寄存器型(SAR)ADC和单斜坡型(SS)ADC组成的混合型高速列级ADC,使转换周期相较于传统的SS ADC缩短约97%；利用SAR ADC的电容实现像素的相关双采样(CDS),在模拟域做差,使CDS的量化时间缩短至一个转换周期,进一步提高了ADC的量化速度；为了保证列级ADC的线性度,提出了一种1-bit冗余算法,可实现+0.13/-0.12 LSB的微分非线性和+0.18/-0.93 LSB的积分非线性。基于180nm CMOS工艺的仿真结果表明,该列级ADC在50MHz的时钟下,转换周期仅为1μs,无杂散动态范围为73.50dB,信噪失真比为66.65dB,有效位数为10.78-bit。

Abstract:

Aiming at the problem that achieving high frame rate for traditional column-level analog-to-digital converter (ADC) in the image sensor is difficult. A hybrid high-speed column-level ADC consisting of a successive approximation register (SAR) ADC and a single slope (SS) ADC is proposed, which reduces the conversion period by about 97% compared with the traditional SS ADC; Achieving correlated double sampling (CDS) of the pixel by the capacitance of the SAR ADC, and makes a difference in the analog domain, so that the quantization time of CDS is shortened to one conversion period, which further improves the quantization speed of ADC; In order to ensure the linearity of column-level ADC, a 1-bit redundancy algorithm is proposed, which can achieve differential nonlinearity of +0.13/-0.12 LSB and integral nonlinearity of +0.18/-0.93 LSB . Simulation results based on 180nm CMOS process show that the column-level ADC has a conversion period of only 1μs, a spurious-free dynamic range of 73.50dB, and a signal-to-noise distortion ratio of 66.65dB, the effective number of bits is 10.78-bit at a clock of 50MHz.