用于图像传感器的自调节加速补偿锁相环设计

A Phase Locked Loop Built-in Self-regulating Acceleration Compensation Circuit for Image Sensoring

摘要:

设计了一款用于高速图像传感器的可自调节、加速补偿CMOS电荷泵锁相环电路,通过在传统锁相环电路拓扑中,附加“双模式”逻辑时控的、低功耗加速充电补偿模块,实现了锁定时间与功耗的双重优化。基于180nm/1.8V CMOS工艺完成锁相环的电路设计和性能仿真,结果表明,基于所提出的加速补偿方案,改进后的锁相环可有效满足图像传感器对低功耗、高速、高频和低噪声输出特性的需求。在输入频率为1GHz的参考信号时,压控振荡器可达到0.55~2.82GHz,即2.27GHz的频率范围,相位噪声为-98.149dBc/Hz@1MHz,锁定时间缩短至5.2μs,整体功耗仅为1.98mW,同时输出的抖动噪声可低至2.81μV/Hz@1MHz,多个性能指标优于所对比的同类锁相环电路。

Abstract:

A self-adjustable CMOS charge pump phase-locked loop (CPLL) circuit with accelerated compensation for high-speed image sensors is designed. Regarding to traditional PLL topology, a "dual-mode" logical clock-controlled and low-power accelerated charging compensation module is added to achieve synchronize optimization in locking time and power consumption. Based on the 180nm/1.8V CMOS process, the circuit design and performance simulation are implemented. The results show that, based on the proposed acceleration compensation scheme, the improved PLL can meet the requirements of high-speed image sensoring application with low noise, low power and high frequency. When a reference signal of 1GHz is input, the proposed voltage-controlled ring-oscillator reaches 0.55~2.82GHz with 2.27GHz frequency range, phase noise is -98.149dBc/Hz@1MHz, locking time is shortened to 5.2μs, average power consumption is only 1.98mW, and the jitter noise in output can be as low as 2.81μV/Hz@1MHz. The proposed PLL has significant superior circuit in power and locking time compared with some other design cases.