一种应用于图像传感器的全数字锁相环设计

A Design of All Digital Phase Locked Loop in Image Sensors

摘要:

针对图像传感器中传统锁相环(PLL)存在的功耗高、抖动大,以及锁定时长等问题,提出了一种基于计数器架构的低功耗、低噪声、低抖动、快速锁定的分数分频全数字锁相环(ADPLL)设计方法。首先,采用动态调节锁定控制算法来降低回路噪声,缩短锁定时间。其次,设计了一个通用单元来实现数字时间转换器(DTC)和时间数字转换器(TDC)的集成,以降低该部分由于增益不匹配引起的抖动。基于180nm CMOS工艺的仿真结果表明,在1.8V电源电压下,该ADPLL能够实现250MHz~2.8GHz范围的频率输出,锁定时间为1.028μs,当偏移载波频率为1MHz时,相位噪声为-102.249dBc/Hz,均方根抖动为1.7ps。

Abstract:

Aiming at the problems of high power consumption, high jitter and long locking-time of traditional phase-locked loops (PLL) in image sensors, a kind of fractional frequency all-digital phase locked loop (ADPLL) is proposed based on a counter architecture. It realizes low power consumption, low noise, low jitter and fast locking design. First of all, the dynamic adjustment lock control algorithm is adopted to reduce the loop noise and shorten the locking time. Secondly, a universal unit is designed to realize the integration of digital time converter (DTC) and time digital converter (TDC), reducing the jitter caused by the gain mismatch. Simulation results based on 180nm CMOS process show that the ADPLL can achieve frequency output in the range of 250MHz~2.8GHz under 1.8V power supply voltage, the locking time is 1.028μs. When the offset carrier frequency is 1MHz, the phase noise is -102.249dBc/Hz, and the root mean square jitter is 1.7ps.