16级模拟电压域CMOS-TDI传感器读出电路

16 Stages CMOS TDI Sensor Readout Circuit in Analog Voltage Domain

摘要:

为了提高推扫(Push-Broom)成像系统的信噪比(SNR),提出了一种可以在模拟域下实现时间延迟积分(Time-Delay-Integration,TDI)功能的CMOS-APS读出电路。区别于以往的数字域算法TDI,在模拟域下累加可以获得更小的噪声和较慢的ADC读出速率。读出电路主要由像素阵列、TDI累加阵列、电荷放大器、S&H单元和行列选择逻辑单元等部分构成。通过与外部FPGA生成的时序逻辑相配合,实现了TDI电压信号的累加。分析了主要单元的噪声源大小和抑制方法,并在CSMC 0.5μm工艺下完成流片,最后通过Labview等测试系统测量了相应的探测器指标并验证了SNR与TDI级数的关系。

Abstract:

To improve the signal noise ration (SNR) of the sensing system in push-broom mode, a new kind of CMOS-APS ROIC is proposed, which can realize time-delay-integration (TDI) function in analog voltage domain. In contrast with the TDI in digital domain, the TDI in analog domain can get lower noise and slower ADC readout rate. The ROIC is mainly composed of pixel arrays, TDI accumulation arrays, charge amps, S&H units and row column selection logic. Under the control of the timing sequence generated by the FPGA out-of-chip, the circuit can realize the accumulation of TDI signal voltage. The noise source from the main parts of the architecture was analyzed, and the corresponding reduction method was proposed. The whole architecture was taped out in 5μm technology of CSMC. Finally, some performance evaluation parameters of the ROIC were measured with the Labview testbench, and the relationship between SNR and the number of TDI was verified.