CCD栅介质工艺对多晶硅层间介质的影响

Effects of Gate Dielectric Process on Inter-layer Dielectric of Polysilicon of Charged-coupled Devices

摘要:

CCD多晶硅交叠区域绝缘介质对成品率和器件可靠性具有重要的影响。采用扫描电子显微镜和电学测试系统研究了CCD栅介质工艺对多晶硅层间介质的影响。研究结果表明: 栅介质工艺对多晶硅层间介质形貌具有显著的影响。栅介质氮化硅淀积后进行氧化, 随着氧化时间延长, 靠近栅介质氮化硅区域的多晶硅层间介质层厚度增大。增加氮化硅氧化时间到320 min, 多晶硅层间薄弱区氧化层厚度增加到227 nm。在前一次多晶硅氧化后淀积一层15 nm厚氮化硅, 能够很好地填充多晶硅层间介质空隙区, 不会对CCD工作电压产生不利的影响。

Abstract:

The inter-layer dielectric of polysilicon remarkably affects the yield and reliability of charge-coupled device (CCD). In this work, the effects of gate dielectric process on the inter-layer dielectric of the polysilicon of CCD were studied by scanning electron microscopy and electrical measurement system. The results show that the gate dielectric process had significant effects on the morphology of polysilicon inter-layer dielectric. The longer the nitride gate-dielectric oxided, the thicker the polysilicon inter-layer dielectric that located near the gate-dielectric. When the oxidation time of silicon nitride was increase to 320 min, the thickness of inter-layer dielectric of polysilicon near nitride gate-dielectric was increased to 227 nm. After the former-layer polysilicon was oxided, a silicon nitride layer with thickness of 15 nm was deposited, which could fill the viods inside polysilicon oxide near gate-dielectric and no adverse effect on the operating voltage of CCD.