The thermo-mechanical stress of both single Through-Silicon Via (TSV) and two-chip-stacked package was investigated with the use of finite element analysis. Stress distributions were demonstrated to be affected by filling materials (copper and tungsten), and the advantages of tungsten-filled TSVs on thermal stress were found. Stress values were proved to be relevant to TSV sizes, such as TSV diameters and aspect ratios of the silicon thickness and the TSV diameter. In order to find the material collocation which has the smallest thermal stress, two-chip-stacked model was applied to simulate the stress in common used materials. It is found that the structure using silicon dioxide as the insulation layer, tungsten as the filling and tin (Sn) as the bonding materials yields the best mechanical performance. Besides, the combination of copper, ABF and tin also performs well in stress.
